Reduced stress and fluctuation for the integrated α-Si TFT gate driver on the LCD

In this paper, an integrated TFT gate driver was designed on the glass substrate not only to decrease the fluctuation at the output, but also to reduce the stress effect on the pull-down branches. The fluctuation in the voltage at the output transistor was attributed to the coupled clocks through the parasitic capacitors in the TFTs. In this study, the voltage gating the pull-down braches was reduced for longer operational lifetime. This scheme was investigated by simulation by Smart-SPICE with an α-Si TFT model from Wintek Inc. at level 35.